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LoadingExplore open-source design tools, verification frameworks, synthesis engines, simulators and physical-design flows — and the chip projects, datasets and research that use them.
Listed — an external project. ChipAI.dev links to it; it does not host or run it.
Integrated — connects to data on ChipAI.dev (Verilator reports on chip projects).
RTL Design
CHIPS Alliance
SystemVerilog parser, style linter, formatter and language server.
RTL Design
Zachary Snow
Converts SystemVerilog to Verilog-2005 so it can feed tools with older front ends.
Functional Simulation
Veripool
Compiles Verilog/SystemVerilog into a fast cycle-based C++ or SystemC model.
Verilator simulation reports can be attached to a chip project and are shown on its page.
Functional Simulation
Stephen Williams
Event-driven Verilog compiler and simulator.
Functional Simulation
GHDL project
VHDL analyser, compiler and simulator.
Functional Simulation
GTKWave project
Waveform viewer for VCD, FST and related dump formats.
Design Verification
cocotb project (FOSSi Foundation)
Coroutine-based testbenches for VHDL and Verilog, written in Python.
Design Verification
Accellera
Reference class library for the Universal Verification Methodology.
Formal Verification
YosysHQ
Front end for Yosys-based formal verification flows.
Logic Synthesis
YosysHQ
Framework for RTL synthesis and netlist manipulation.
Logic Synthesis
UC Berkeley
System for sequential logic synthesis and formal verification.
Physical Design
The OpenROAD Project
Automated RTL-to-GDSII physical design toolchain.
Physical Design
Efabless
Configurable RTL-to-GDSII flow built on OpenROAD, Yosys and Magic.
Physical Design
Matthias Köfferlein
Layout viewer and editor with DRC and LVS scripting.
Physical Design
Open Circuit Design
VLSI layout tool with interactive DRC and extraction.
Static Timing Analysis
Parallax Software / The OpenROAD Project
Gate-level static timing verifier used inside OpenROAD.
Power Analysis
Parallax Software / The OpenROAD Project
Static and activity-annotated power estimates from the OpenSTA timing database (report_power).
DFT and Testing
AUCOHL
Design-for-testability toolchain: scan-chain insertion and test-pattern generation.
FPGA Development
YosysHQ
Portable FPGA place-and-route tool for open FPGA flows.
FPGA Development
openFPGALoader project
Universal utility for programming FPGA boards.
FPGA Development
Enjoy-Digital
Framework for building FPGA SoCs from reusable cores.
Workflow Automation
FOSSi Foundation
Package manager and build-system front end for HDL code.
Workflow Automation
FOSSi Foundation
Python library giving one interface to many EDA tool flows.
This directory lists open-source projects only and links to each project's own site; licences shown are each project's declared licence — confirm on the project before use. ChipAI.dev does not distribute or execute these tools, and commercial EDA software is not offered here.