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BrowseChips Models Datasets All repositories EDA tools Research DocsSearch anything: Ctrl/⌘ K

RTL & IP Core Projects — Verilog, SystemVerilog, VHDL, Bus Interfaces · ChipAI.dev

Chips
RTL & IP Cores

RTL & IP Cores

Discover reusable hardware modules, digital logic implementations, and verified semiconductor IP blocks.

Source & verification

Developing projects are git repositories: the Files tab offers directory navigation, branches, repo-wide file search and a text viewer for Verilog, SystemVerilog and VHDL, with a README preview on the project page.

Verilator simulation reportsAvailable
Verible lintingPlanned
Icarus Verilog runsPlanned
cocotb test executionPlanned
Yosys synthesis runsPlanned

Verilator reports are uploaded by the project; ChipAI.dev does not run the simulation. Planned items are not executed on the platform yet.

RTL & IP Cores projects 0

Search chip projects

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HDL / style

No published chip projects yet — here is how to add the first one.

01
Request a contributor role
From your profile — a moderator approves it.
02
Run the publish wizard
Type, repository, architecture metadata — publish a chip project.
03
Push your RTL
Clone the project's git repository and push rtl/, tb/ and reports.

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